PETSc is a suite of data structures and routines for the scalable (parallel) solution of scientific applications modeled by partial differential equations. It supports MPI, and GPUs through CUDA, HIP or OpenCL, as well as hybrid MPI-GPU parallelism.

Application optimization using FPGAs

A multiscale computational framework for coupling the multiple length scales in chemical vapor deposition (CVD) processes is implemented for studying the effect of the prevailing conditions inside a CVD reactor (macro-scale) on the film growth on a wafer with predefined topography (micro-scale). A multi-parallel method is proposed for accelerating the computations. It combines domain decomposition methods for the macro-scale (reactor scale) model, which is based on partial differential equations (PDEs), and a synchronous master-worker scheme for the parallel computation of the boundary conditions (BCs) for the PDEs; BCs are coming from the micro-scale model describing film growth on the predefined topography.

A set of linear and nonlinear stability analysis tools have been developed to analyze steady state incompressible flows in 3D geometries. The algorithms have been implemented to be scalable to hundreds of parallel processors. The linear stability of steady state flows are determined by calculating the rightmost eigenvalues of the associated generalize eigenvalue problem. Nonlinear stability is studied by bifurcation analysis techniques. The boundaries between desirable and undesirable operating conditions are determined for buoyant flow in the rotating disk CVD reactor.

We present a numerical study of the structure and stability of laminar isothermal flows formed by two counterflowing jets of an incompressible Newtonian fluid. We demonstrate that symmetric counterflowing jets with identical mass flow rates exhibit multiple steady states and, in certain cases, time-dependent (periodic) steady states. Two geometric configurations were studied based on the inlet jet shapes: planar and axisymmetric. Stagnation flows formed by planar counterflowing jets exhibit both steady-state multiplicity and time-dependent behaviour, while axisymmetric jets exhibit only a steady-state multiplicity. A linearized bifurcation and stability analysis based on the continuity and Navier–Stokes equations revealed transitions between a single (symmetric) steady state and multiple steady states or periodic steady states. The dimensionless quantities forming the parameter space of this system are the inlet Reynolds number (R$e$) and a geometric aspect ratio ($\alpha$), equal to the jet inlet characteristic length (used for calculating R$e$) divided by the jet separation. The boundaries separating different flow regimes have been identified in the (R$e$, $\alpha$) parameter space. The resulting flow maps are useful for the design and operation of counterflow jet reactors.

This paper presents an approach for determining the linear stability of steady states of partial differential equations (PDEs) on massively parallel computers. Linearizing the transient behavior around a steady state solution leads to an eigenvalue problem. The eigenvalues with the largest real part are calculated using Arnoldi's iteration driven by a novel implementation of the Cayley transformation. The Cayley transformation requires the solution of a linear system at each Arnoldi iteration. This is done iteratively so that the algorithm scales with problem size. A representative model problem of three-dimensional incompressible flow and heat transfer in a rotating disk reactor is used to analyze the effect of algorithmic parameters on the performance of the eigenvalue algorithm. Successful calculations of leading eigenvalues for matrix systems of order up to 4 million were performed, identifying the critical Grashof number for a Hopf bifurcation. Copyright © 2001 John Wiley & Sons, Ltd.

Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency and power consumption.

Field Programmable Gate Array or FPGA is introduced in the year 1985 and it is getting popular day by day due to its properties like design to reuse and flexibility. As compared to microprocessor, FPGA have high performance and configurability. When compared with application specific integrated circuit (ASIC), FPGA reduces development time, non-recurrent engineering (NRE) costs. The unique property which differ it from ASIC is its reconfiguration. The recent trends in FPGA architecture are in the direction which reduces the gap between the ASIC and FPGA. This paper will discuss on the classification of FPGA based on their routing architecture and the recent trends in the field of Physics, computation, defense, space research, etc., which are focusing on betterment of the existing technology.

This training is for engineers who have never designed an FPGA before. You will learn about the basic benefits of designing with FPGAs and how to create a simple FPGA design using the Intel® Quartus® Prime software.

This tutorial is organized in 5 parts and is designed to walk you through all the key aspects of the Vitis flow.